1. Field of the Invention
The present invention generally relates to computer systems. More specifically, the present invention relates to optimization of access in a synchronous dynamic random-access memory (SDRAM).
2. Description of the Related Art
Graphics-intensive applications for computers such as personal computers (PC""s) are becoming increasingly more popular. Such applications include high-end computer-aided drafting (CAD) applications, games, real-time video applications, as well as other applications. As these applications become more complex, they require the computers on which they are executed to render graphics at an ever increasing rate. Furthermore, as the typical resolution of computer screens has increased from 640xc3x97480 pixels (horizontal times vertical) to 800xc3x97600, 1024 xc3x97768 and beyond, and increased color information per pixel from two bits to 24 bits to 32 bits and beyond, the processing demand placed on the computers for fast graphics execution has also grown. The typical computer relies on a graphics card (also known as a video card, graphic accelerator card, or a display adapter, among other terms) for assistance in the display of graphics on a display device. A graphics card generally includes one or more specialized processors that are manufactured specifically for graphics rendering and processing graphics-related. The graphics card also typically includes memory, ranging from one, two, four, eight, sixteen megabytes and up, so that a complete screen of graphics information, known as a frame, can be stored by the graphics card. Thus, this memory is generally known as a frame buffer of the graphics card. Graphics xe2x80x9ccardsxe2x80x9d may also be integrated within a single chip on a motherboard of a computer. A graphics card, potentially along with other components, makes up the graphics subsystem of a computer.
Initially, the memory of a graphics card was of the common type of dynamic random-access memory (DRAM) which is used by computer processors to hold data during processing. However, the access of data, i.e. the reading and writing of data to memory addresses, tends to be a slow process relative to the other processor components. Thus, as improvements in memory accessing speed have occurred in general memory hardware, such as the introduction of synchronous dynamic random-access memory (SDRAM), such improvements have also been included into graphics cards and graphics processing subsystems.
Specifically, a 2-bank SDRAM has been implemented in a graphics card to improve the memory access. With dual bank SDRAM, two different pages in memory may be open at the same time, one in each bank. FIG. 1 shows a prior art checkerboard arrangement 100 for a memory access using a 2-Bank SDRAMS. In this checkerboard arrangement 100, two adjacent locations are stored in two different memory banks. When drawing a figure, both banks 0 and I contribute one row of data, thus reducing latency in data accessing. The 2-bank SDRAM still does not possess adequate data throughput for modern graphics applications.
Accordingly, it would be advantageous to provide a system to further speed memory access in a graphics-intensive processor. It is thus to such a system that the present invention is directed.
The present invention discloses an enhanced checkerboard arrangement for 4-bank SDRAM. This enhanced checkerboard arrangement takes advantage of 4-bank SDRAM and improves performance in a computer system by reducing latency in memory access. The enhanced checkerboard arrangement groups memory banks in such way that four SDRAM memory banks form a basic block with four squares, where each square represents one memory bank. This arrangement particularly facilitates the drawing of small objects.
There are two basic SDRAM memory blocks, each formed by four memory banks. These two basic blocks are further arranged to form an enhanced checkerboard pattern composed of 16 squares, where four distinguished memory banks are aligned vertically. This arrangement facilitates the drawing of large objects.